Surprise, surprise! :)
I have just redesigned the timing to run the Fast RAM at 50 MHz. The board still uses 60 ns DRAM chips; due to this one wait state is inserted in every Fast RAM access cycle. The results are not bad: it produces ~4.4 MIPS at 50 MHz (it was 3.3 MIPS at 32 MHz with 0 wait state 60 ns DRAM).
The waitstates are clearly visible on the timing diagram below: one CPU cycle takes 10 clock cycles instead of 8.
Stay tuned. More news are coming soon! :)