Sunday, July 12, 2015

Amiga 500 68HC000 accelerator running at 50 MHz

Surprise, surprise! :)

I have just redesigned the timing to run the Fast RAM at 50 MHz. The board still uses 60 ns DRAM chips; due to this one wait state is inserted in every Fast RAM access cycle. The results are not bad: it produces ~4.4 MIPS at 50 MHz (it was 3.3 MIPS at 32 MHz with 0 wait state 60 ns DRAM).

The waitstates are clearly visible on the timing diagram below: one CPU cycle takes 10 clock cycles instead of 8.

Stay tuned. More news are coming soon! :)


  1. This is pretty amazing work! Do you have any plans to do a Zorro slot expander in the future? Keep up the good work! I'm tracking your projects on my own site:

  2. Thank You for the comment! :)

    Currently I'm focusing on the A500, I need to debug the hardwares 100%.

  3. Amazing project! Don't spare the juicy details as it progresses towards completion. :D

  4. 5 cards have been shipped to testers. Now waiting the live test results before beginning the (mass) production.