Amiga 500 68HC000 accelerator running at 50 MHz

Surprise, surprise! :)

I have just redesigned the timing to run the Fast RAM at 50 MHz. The board still uses 60 ns DRAM chips; due to this one wait state is inserted in every Fast RAM access cycle. The results are not bad: it produces ~4.4 MIPS at 50 MHz (it was 3.3 MIPS at 32 MHz with 0 wait state 60 ns DRAM).

The waitstates are clearly visible on the timing diagram below: one CPU cycle takes 10 clock cycles instead of 8.

Stay tuned. More news are coming soon! :)

Amiga 500 28 MHz accelerator with DRAM

Hello Boys and Girls! [Melon - Prism :) ]

We have reached the next phase. Finally, 3 MIPS is "coming out" from the 68HC000 which is running at 28 MHz. The design uses 60 ns 0 wait state DRAM.

A phase correct, stable 28 MHz clock is still missing as it is not available on the expansion connector. Currently the 28 MHz clock signal is coming directly from the main quartz oscillator, from the motherboard (see the green wire). Once I obtain a proper PLL clock multiplier, this wire will be eliminated.

28 MHz 68HC000, 0 wait state 8 MB DRAM, 3 MIPS, autoconfig

And as always, some screenshots (SysInfo speedtest and Bustest results):

I have also tried to reach the barriers of the 68HC000CFN16. It works rock stable at 50 MHz and it is cold like an ice. :) Don't forget, it is a CMOS design and draws almost zero current (the power consumption of CPU is ~1.3 W). For the 50 MHz design SDRAM will be required in order to get out everything from the CPU (at 50 MHz the CPU cycles are ~45 ns (see the screenshot below), which don't fit the 60 ns RAM access time:

This design uses the same PCB as the 14 MHz version (rev 2). The measurements are done with a Zeroplus logic cube.

On the screenshot above the burst refresh cycles are shown. The next phase will be a completely new board design with IDE, CF, Flashkick, 8 MB RAM, 68HC000 @28 MHz etc.

Stay tuned!  :)