This is not a brand new realization, but in the past months I didn't have time to publish this post. The first fully functional prototype has been assembled around January 2014.
This project has been started in September, 2013 when the first experiments began with the Xilinx XC 9572 CPLD.
The first step was to build a JTAG interface cable. It is based on the official Xilinx programmer cable. The schematic is available on the Xilinx site. Of course, a TQFP adapter was required in order to work with an SMT device on a breadboard.
ISE Design Suite 14.1 has been used in the testing and development phase (Verilog). Once the initial tests succeeded, the first real project was of course the Autoconfig realization.
When it worked properly, the next step was a DRAM controller on a breadboard, but now with a CPLD.
When it worked properly, the next step was a DRAM controller on a breadboard, but now with a CPLD.
The noise problem appeared again,
as in the TTL design. Some timing tricks have been used to be able to
complete the DRAM tests before designing the first PCB version.
Below You can find some screenshots of the working system. It accepts regular 72 pin SIMM and EDO RAM modules. All tested memory modules are working 100%.
