Long time
ago (more precisely around 1993) when I bought my first Amiga 1200 it
was a wonderful machine for a reasonable price (~800 DEM): fast, 32 bit CPU, 2 MB RAM, integrated IDE controller, everything I have ever dreamed about. But I soon confronted the reality: it hasn't got enough
memory available, the HDD is not included in the base product price etc. The 2.5" 120 MB HDD costed
600 DEM in those times (~300 USD). It was a "regular" price for a 2.5" device then.
But
the RAM was a completely different thing. 1 MB SIMM module costed ~70 DEM
(~30-40 USD), while a 4 MB RAM expander for the Amiga 1200 400-500 DEM! 4x 70 = 280 DEM. Perfect, Commodore f***d it up again: they didn't add a standard SIMM socket to the motherboard, so You have no chance to add a cheap RAM module to the system.
Are You wondering why Commodore didn't survive the 90's and why it couldn't become a leading PC manufacturer (PC is not equal with IBM compatible in this context, but a Personal Computer)? Partial answer is: it costed a lot more than any "Taiwan assembled" IBM clone. Only Apple was able to sell the 2-3x overpriced Macintosh machines... till 1997... then there was a big chance they will also follow the C=... But this is a completely different story. Lets go back to the original topic.
Are You wondering why Commodore didn't survive the 90's and why it couldn't become a leading PC manufacturer (PC is not equal with IBM compatible in this context, but a Personal Computer)? Partial answer is: it costed a lot more than any "Taiwan assembled" IBM clone. Only Apple was able to sell the 2-3x overpriced Macintosh machines... till 1997... then there was a big chance they will also follow the C=... But this is a completely different story. Lets go back to the original topic.
In
1993 I've got the original John Kamchen 8 MB Fast RAM expander
schematic with description. The next step was clear: adapt it somehow to
fit in Amiga 1200. But it wasn't as easy as it looked to be. It was designed for an Amiga 500 which is a 16 bit machine while Amiga
1200 has a 32 bit CPU. Duhh!
I
was seeking for help everywhere: asked various electronic engineers,
everybody who ever worked with digital electronic... Needless to say,
no one was able to help me to redesign the project, or at least to understand
how it works. So the memory expander project was cancelled, I sold my Amiga 1200 in 1995 with
it's original 2 MB RAM and 120 MB HDD to pull out some money from the obsolete thing.
In
2000 I began again to collect Amiga hardwares, including A2000, A1200,
A4000, A500 etc. A2000 has an original C= fast RAM expander (A2058) etc.
It
2011 I've got an idea: why to not try again to build the original John
Kamchen RAM expander, but now in original form, for an Amiga 500?
I've installed all components on a veroboard.
The first test results were promising: the Amiga booted up successfully, the CPU did not burn out etc. ;)
I have checked the RAM at location $200000 with MasterSeka 1.8 and found it! It was readable and writable, but the content was always corrupt. It forgot the data soon after I have entered it. I have tried to fix the hardware for 2 weeks, without any success. And I gave up... till January 2013.
Then I began to build a new RAM board with an entirely new approach. It was clear: without completely understanding the theory of the operation of dynamic RAM and the MC 680000 on a hardware level it is impossible to realize a such project.
The first thing was to collect all available manuals about DRAMs and MC 680000 CPU. In the first phase I have designed a simple 8 bit DRAM controller connected to Amiga, located at $20000.
This testing and development phase lasted cca. 2 months, until I have fully understood the DRAM systems and implemented the refresh circuitry. The refresh circuit on the original John Kamchen schematic does almost nothing: it activates the refresh cycle when the CPU accesses the Chip RAM (every 20 ms when interrupts are executed in idle state). But it is not enough at all. Each DRAM cell requires refresh in every 8 ms, but the original design executes one refresh cycle in every 20 ms (a burst like, but it never refreshes all cells within the 8 ms period)..
So, I have designed a completely new refresh circuit and the content of RAM has not been corrupted anymore.
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| The $AA is the valid upper Byte content of the DRAM |
The next phase was to implement the 16 bit version on a breadboard. First, a 2 MB version:
And a 4 MB version:
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| 16 bit 4 MB breadboard version |
And the problems began. The board worked properly for hours, but sometimes the Amiga crashed strangely. It became clear the system crashed when I launched Turbo Imploder, Hippoplayer or any other music player software.
Meanwhile I have tried every possible and impossible combinations to fix it. A new, veroboard based prototype has been built to check the noise level with different PCB layouts. The veroboard produced 3-4 times less noise than the plastic breadboard version but the same bug was still there.
After 6 weeks of testing and debugging (daily 8-10 hours) it became clear there is a mistake in my design: I didn't check carefully the CPU timing diagrams and I have used the same timing for bus master cycle case 2 as for case 1 which led to a shortened RAM access cycle (200 ns RAM access cycle is used, the remaining cycle is for the refresh). You can see the strange thing on the screenshots below: when the code is executed step by step, it works perfectly. In high speed execution the CPU fetches wrong data from the RAM.
For some strange reason the problem appeared only after accessing the $a00000 or $b00000 area: the next fetched instruction was corrupt (some Bytes have been skipped).
For some strange reason the problem appeared only after accessing the $a00000 or $b00000 area: the next fetched instruction was corrupt (some Bytes have been skipped).
Once the reason was found it took only 15 minutes to fix it. But by then I already spent 420 hours trying to find the cause of problem. Great!
Currently I'm testing the 4 MB RAM board combined with the IDE interface. On the picture below You can see the RAM board fitted in Amiga 500.
Currently I'm testing the 4 MB RAM board combined with the IDE interface. On the picture below You can see the RAM board fitted in Amiga 500.
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| Schematic diagram of the 4 MB Fast RAM expander |
I have also started to design the PCB version. Further plans:
-design the Autoconfig version
-implement logic functions with PALs to reduce the number of TTLs
-combine it with the IDE controller
